By Ron Wilson
Integrated System Design
Posted 03/15/01, 11:26:30 AM EDT

Munich, Germany - DATE Conference - March 15, 2001 - CEOs from three of the big four EDA tool vendors joined forces in a DATE panel here this afternoon to survey the emerging challenges — and possible solutions — in the industry's near future.

Ray Bingham of Cadence, Aart de Geus of Synopsys, and Wally Rhines of Mentor Graphics saw similar challenges, all related to the growing importance of System-on-Chip (SoC) design. But they diverged considerably in their approach to solutions.

Bingham pointed to the emergence of consumer markets — with their emphasis on time to market and cost — as a fundamental driver of change. To meet the challenge, he said, Cadence's view of the market has changed from licensing tools to driving convergence of Cadence tools, supply chain forces and the customer's own expertise. In order to support this triad, Bingham claimed, Cadence has had to extend the range of its tool set. The new environment will employ hierarchy to cope with the breadth of complexity in SoC designs at the front end, while drilling deeper into the physical detail of designs to ensure closure at the back end.

Synopsys's de Geus examined the specifics of the design gap in more detail, suggesting six active areas of investigation. These included timing closure, verification, IP-based system design, test strategy, power management and signal integrity. The CEO suggested that progress would come from pulling together specific solutions to these issues.

Rhines, in contrast, zeroed in on verification as the outstanding challenge. Verification consumes up to 70 percent of design time, and is growing toward a similar portion of tool spending, Rhines said. He claimed that formal verification, as a necessary tool for coping with top-level complexity, "has taken off like a rocket in the last 12 to 18 months." But Rhines's favorite verification tool is emulation. Not commenting on the ongoing litigation between Synopsys and Cadence over emulation patents, Rhines said that hardware emulation was vastly more powerful than software techniques. He projected that in the future, local emulation hardware would be a feature of virtually every chip designer's workstation, backed up by a central emulation server within the server farm.The CEOs also differed significantly in their orientations for applying new tool strategies to the emerging challenges.

Bingham and de Geus cited the role of partnership with the customer — and application understanding — in successful design. While Cadence has spun off its design services unit, Bingham still emphasized the customer's key role in successfully deploying new tools. And de Geus went on the record as well on the importance of design services in serving the increasingly application-specific needs of the market, "The services business is necessary to connect our capabilities to specific applications domains," he claimed.

Only Rhines differed in this area, taking a very traditional approach to the services question. Rather than investing in detailed application-specific knowledge, Rhines said, "our job is to find common needs across our customers, and to deliver economies of scale in solutions."

Looking at the future in somewhat more abstract terms, de Geus projected that as designers struggled with increasingly heterogeneous but coupled SoC networks, they would turn to platform-based design "to narrow the range of choices." The problem, of course, is to simplify the design without reducing the power or flexibility of the platform too much, he said.

Yet, de Geus appeared to dash one fond hope of EDA users. Asked if he believed there would ever be a plug-in environment that could readily include new point tools, de Geus simple said "It will never happen. We will never achieve a plug-in environment, because the rate of change in the problem is too great. We simply can't provide an anchor of main tools and attach anything that comes along to them. There will be too many needs for new formats and additional data types."

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